1. Field of the Invention
The present invention relates to an non-volatile semiconductor memory such as a flash memory that rewrites memory information of its memory cells by injecting electric charge into their floating gates, and more particularly to an improvement for preventing so-called threshold reduction in memory transistors, a phenomenon that data read from the memory cells can be inverted because of the time-varying reduction in electric charge injected into the floating gates.
2. Description of Related Art
FIG. 18 is a block diagram showing a part of an internal configuration of a common conventional flash memory disclosed, for example, in Japanese patent application laid-open No. 56-71898/1981. In FIG. 18, the reference numeral 1 designates a memory cell area including an array of a plurality of memory cells; and reference numerals 2s each designate a read memory bank composed of a plurality of memory cells (read memory cells) formed in the memory cell area 1. Reference numerals 4s each designate a read bit-line selector connected to one of the read memory banks 2 for selecting one of the bit lines connected with the read memory cells in the read memory bank 2 in accordance with a first part of the address data AD which is input when the data read access takes place to the flash memory; and 6s each designate a read sense amplifier connected to one of the read bit-line selectors 4 for comparing the voltage level of the bit line selected by the read bit-line selector 4 with a predetermined read threshold voltage, and for outputting read data RD of a voltage level determined by the relationship between these compared voltages. The reference numeral 8 designates a word-line decoder that receives, when data read access takes place to the flash memory, a second part of the address data AD which remains after the first part of the address data is supplied to the read bit-line selector 4, and selects, in response to the second part of the address data AD, one of a plurality of word lines connected to the memory cell area 1.
Next, the operation of the conventional flash memory will be described.
The flash memory with such floating gate electrodes injects electric charge into the floating gate electrode of each read memory cell in order to set the threshold voltage of the read memory cell. Generally, since the threshold voltage for turning on the transistor of the memory cell increases with the injection of the electric charge into the floating gate electrode, no current flows in this case even when the read sense amplifier 6 is connected to the memory cell, and hence the voltage level of a read signal becomes high. On the contrary, since the threshold voltage for turning on the transistor of the memory cell is low unless the electric charge is injected into the floating gate electrode, a current flows when the read sense amplifier 6 is connected to the memory cell, and hence the voltage level of the read signal becomes low. Then, the read sense amplifier 6 compares the voltage level of the read signal with its threshold voltage VTH which is represented by a solid line in FIG. 19, and outputs "0" when the level of the read signal is higher than the threshold voltage VTH, whereas it outputs "1" when it is lower than the threshold voltage VTH. In FIG. 19, the horizontal axis represents a voltage Vcc supplied to the flash memory, and the vertical axis represents the voltage levels of the threshold and read signal.
Since the conventional semiconductor memory with the floating gate electrodes is thus arranged, a phenomenon can occur that the electric charge injected into the floating gate electrode of each read memory cell leaks after a certain time period, and hence the voltage level of the read signal drops below the threshold voltage VTH of the read sense amplifier 6 as shown in FIG. 19, so that the read data RD of the read memory cell which originally stores "0" is inverted to "1".
In view of this, manufactures of such semiconductor memories try to prevent the problem of the threshold reduction in the memory transistors of the conventional semiconductor memories by shipping only semiconductor memories that meet specified characteristics in their examinations. Such a countermeasure against the threshold reduction in the memory transistors of the semiconductor memories can only experientially reduce a possibility of its occurrence in the field they are actually used, and limits their yield, as well.